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SNAD02C 8-channel 10-bit adc ======== contents ======== 1. gene r a l d e sc r i pti o n ............................................................................................................ ........................... 3 2. feat u r es ....................................................................................................................... ............................................. 3 3. ap pli c atio ns ................................................................................................................... ....................................... 3 4. bloc k d i a g r a m .................................................................................................................. ................................... 4 5. pi n as si g n me nts ................................................................................................................ ................................... 4 6. fu n c ti o n a l de s c ript i o n s ........................................................................................................ ..................... 5 6.1. i nterface f ormat ............................................................................................................................... ... 5 6.2. c hannel s et ti ng ............................................................................................................................... ..... 7 6.3. c ontrol r egi s ter s etting ................................................................................................................... 7 6.4. ad c r ead t im i n g ............................................................................................................................... ... 8 6.5. t iming of d igi t al i nput r ea ding ........................................................................................................ 9 6.6. p ower d own & c hannel w ake -u p .................................................................................................. 10 6.7. b andgap refe rence ............................................................................................................................. 11 6.8. i nput c hanne l pa d (c hann el 0~6) ................................................................................................. 12 6.9. b attery m oni toring (c hannel 7 only ) ......................................................................................... 13 7. elect r i cal charac t e ri sti c s ..................................................................................................... ............. 14 8. ap pli c atio n c i r c u it s ........................................................................................................... .......................... 15 9. e x a m ple p r o g r am s ............................................................................................................... .......................... 16 9.1. p rogram 1: s et c onfigurat ion of sna d 0 2c ............................................................................... 23 9.2. p rogram 2: r ead adc result from c han nel 1 ........................................................................... 23 9.3. p rogram 3: r ead d igital i n p ut data from c h 4, c h 3, c h 2 ....................................................... 23 9.4. p rogram 4: p owe r - down sna d 02c and h ost , and w ak e - up ................................................... 24 9.5. p rogram 5: b attery l ow d etection .............................................................................................. 24 10. pa d d i ag r a m .................................................................................................................... ............... 26 version: 1.3 july 31, 2003 1
SNAD02C 8-channel 10-bit adc amendment history v e r s i o n d a t e d e s c r i p t i o n ver 1.1 february 12, 2003 first issue. ver 1.2 march 18, 2003 page3: wording modification in features list page8: modify table-3 control register setting pa ge 10 : mod i fy f i g u r e -1 0 page11: ?enters into power down mode at the 8 th clock cy cle? page11: more descript about power-down mode setting ver 1.3 july 31, 2003 1. add version code ?c? of chip no. 2. page23: mb=1 3. this spec is modified form snad02_v1.2 note: this document is used to identify the different version ?b? & ?c? of snad01, the most important is standby current and power down setting between version ?b? & ?c?. for the detail please refer to related section. version: 1.3 july 31, 2003 2
SNAD02C 8-channel 10-bit adc 1. general description SNAD02C is a low cost seria l 10-b i t s adc with 8 individu al inp u t ch anne ls. each chan n e l can be indep ende ntly programmed to a dig i t a l or a nalog input mod e . in the ana log input mo de, th is sing le- ended chan nel accepts an a nalog in put sign al fr om 0 to v ref and co n v erts the sig nal into 12- bit d i g i tal code s (w ith 1 0 -bit a ccur a cy guaran teed ). in the d i git a l inp u t mod e , t he cha n n e l can be treated as digita l input po rt and the log i c leve l appe ars a t the ch annel ca n be acqu ire d . s n ad02c has a syn c hr onous 3-wire s ser i al inter f ace. th roug h this inte rfa c e, the host cpu can ea sily contro l SNAD02C. during a-to- d conver sio n , the typical current co nsu m ption is 50 0ua at 25 khz thr ough put -rate and +3v power supply. sna d 02c in clud es a pow er- down mode, which r edu ces maximum cur r ent consumption less than 1ua. the refe ren c e volta ge can be varie d between 1v and +v cc , providing a corre spo n d ing inpu t voltage ran g e of 0v to v re f . snad02 c also has a n on- ch ip 1.1 7 v ban dgap referen c e th at can be utilized for consta nt vo lta ge input (e specially fo r b a ttery monit o ring ap plica t ion s ). th e bandga p reference circuitry consumes 300 2. fea t ures ? ? ? ? ? ? ? 3. applica t ions ? ? ? ? ? ? ? version: 1.3 july 31, 2003 3
SNAD02C 8-channel 10-bit adc 4. block diagram 8-channels analog/digital input mux 12 bit sar adc serial interface and control logic vrh start clk dio avdd vdd d avss vssd ch0/di0 ch1/di1 ch2/di2 ch3/di3 ch4/di4 ch5/di5 ch6/di6 ch7(bat)/di7 1.2v bandgap reference figure-1 block diagram of adc 5. pin assignments pin name i/o description ch[7] ~ ch[0] i analog input / digital input ref i reference voltage of analog signal vdd i positive power v s s i n e g a t i v e p o w e r avdd i positive power of analog circuit avss i negative power of analog circuit start i command initialization signal (from host controller) clk i clock of dat a communicat i on an d ad conversion (fr o m host controller) dio io data input and output of data communication table-1 version: 1.3 july 31, 2003 4
SNAD02C 8-channel 10-bit adc 6. functional descriptions host cpu output port1 output port2 i/o port snad02 start clk dio start clk dio vdd avdd ref vdd ` vss avss ch[0] ch[1] ch[7] analog/digital signal 0.1u f figure-2 interface w i th host cpu 6.1. interface format channel setting control register setting hiz cm2 cm1 cm0 ph pl rf mb x x x x x xx x x dio digital input reading power down clk start hiz cm2 cm1 cm0 ch[7] ch[6] ch[5] ch[4] ch[3] ch[2] ch[1] ch[0] x xx x x dio hiz cm2 cm1 cm0 di[7] di[6] di[5] di[4] di[3] di[2] di[1] di[0] di[3] di[7] di[6] di[5] di[4] dio port input port output port input hiz cm2 cm1 cm0 pds pds pds pds pds pds pds pds pds pds pds pds pds dio port output port input port input figure-3 timing diagram of whole commands version: 1.3 july 31, 2003 5
SNAD02C 8-channel 10-bit adc (1) dio is hiz while start is high. (2) the interface logic begins to interpret a command at the falling edge of the start signal. (3) the command id (sent by host) is received in the first three clock cycles from dio. (4) the op erat io ns include c hanne l sett in g, adc rea d ing, dig i ta l input re adin g and power down. (5) dio becomes to hiz while start returns to high. command id operation 000 power down (0) 001 channel attribute setting (1:analog, 0:digital) 010 channel wakeup function setting (1:enable, 0:disable) 011 control register setting 1 0 0 a d c c o n v e r s i o n 101 digital input reading 1 1 0 r e s e r v e d 111 power down (1) table-2 command description table a. 000/111: adc enters into power down after receiving this command. b. 001: set the attrib ute o f e a ch chan nel to be a n ana log or a dig i ta l inp u t wit h th e seq uence of channel 7 to 0. (1:analog; 0:digital) c. 010: se t th e wakeup fun c tion of each channe l to be enabled o r d i sabled w i th t he seque nce of channel 7 to 0. (1:enable; 0:disable) d. 011: setting the values of control registers. e. 100: adc st arts to conv ert th e an alog sign al of the se lecte d ch anne l a f ter re ce iving this command. f. 101: adc st arts to re ad t he dig i ta l inp u t of every channe l with t he sequ ence of chann el 7 to 0. g. 110: adc enters into testing mode. version: 1.3 july 31, 2003 6
SNAD02C 8-channel 10-bit adc 6.2. channel setting clk start channel setting hiz cm2 cm1 cm0 ch[7] ch[6] ch[5] ch[4] ch[3] ch[2] ch[1] ch[0] x xx x x dio port input figure-4 the timing diagram of channel attribute/w akeup setting (1) command 001: channel attribute setting. (2) command 010: wakeup function setting. in at trib ute settin g , ? 1 ? m eans ana log and ? 0 ? mea n s dig i ta l. in wake up set t i ng, ?1? mea n s enab le and ?0? mea n s disab l e. after all of th e chann els a r e set, th e dio port remains inp u t mod e and all the following data are ignored. 6.3. control register setting clk start control register setting hiz cm2 cm 1 cm0 ph pl rf mb x x x x x xx x x dio port input figure-5 the timing diagram of control registers setting (1) command id: (011) (2) 4-bit dat a be hind command id are loa ded into co nt rol r egister s with t he seq uence of ph, pl, rf and mb. (3) the function of each control registers are as table-3. version: 1.3 july 31, 2003 7
SNAD02C 8-channel 10-bit adc n a m e f u n c t i o n ph set the pu ll-u p resistor o f t he chan nel in digital inpu t mode. 1:on, 0:off. pl set the pull-down resistor of the channel in digital input mode. ?1?: on, ?0?: off. rf, mb set the reference source (from internal bandgap or ?ref? pin) rf=0, mb=1: reference voltage from ?ref? pin rf=1, mb=0: reference voltage from internal bandgap table-3 note: 1. the condition of both ph=1 and pl=1 is prohibited. 2. pull-up a nd pull-d o wn resistor s ar e not a c ti vat ed while the corre spon ding cha nne l is set a s analog input m ode. 3. before into power down m ode, the ?rf ? and ?mb? register m u st set up ?0? , otherwise the standb y current will m o re than 1ua. 6.4 . adc read timing start adc reading hiz cm2 cm1 cm0 id2 id1 id0 x x d9 d8 d7 d2 d6 d5 d4 d3 dio d0 d1 port input port output clk figure-6 the timing diagram of adc reading version: 1.3 july 31, 2003 8
SNAD02C 8-channel 10-bit adc (1) command id: (100) (2) 3-bit channel number data behind command id. (3) the analog sign al of th e se le cted ch annel is sa mpled to ad c. adc ref e rs the ref e r ence voltage an d converts t he sample d analog sig nal to d i git a l domain by succe ssive- approximation method. (4) the 10- bit o u tput data (r esult of co nversion) o f a dc is sent t o dio port f r om msb and i s trigg e red by clk. the m a ximum clock fre quen cy is 500 khz @ 2.7v. (maximum conversion rate=25khz) (5) after the 10- bits adc da t a has b een sent out , if t h e start is ke pt in low an d clk is kep t in high/low tra n sit i on , t hen the data wit h un certa i n value are kep t ap pear ing on dio. t h e se data can just be ignored. channel id[2:0] selected channel 0 0 0 c h 0 0 0 1 c h 1 0 1 0 c h 2 0 1 1 c h 3 1 0 0 c h 4 1 0 1 c h 5 1 1 0 c h 6 1 1 1 c h 7 table-4 channel selection table 6.5. timing of digital input reading clk start digital input reading hiz cm 2 cm 1 cm0 di[7] di[6] di[5] di[4] di[3] di[2] di[1] di[0] di[3] di[7] di[6] di[5] di[4] dio port output port input figure-7 the timing diagram of the digital input reading version: 1.3 july 31, 2003 9
SNAD02C 8-channel 10-bit adc (1) command id: (101). (2) the digital data of each channel is sent to the dio port with the sequence of channel 7 to 0. (3) after a ll of t h e ch anne ls a r e read , if th e start is ke pt in low an d clk is kep t in h i gh/low transition, t h e dig i ta l da ta of ea ch cha nnel is sen t t o the dio po rt aga in with the seque nce of channel 7 to 0 cyclically. (4) pulling start to high to terminates this digital input reading. note: once a ch anne l is programm ed as ana log type, th e corre spond ing dat a is ?0? in d i g i tal in put reading com m and. 6.6. pow e r dow n & channel wake-up 00 0 11 1 snad01 enters into power-down mode start clk dio dio figure-8 the timing diagram of pow er dow n command start clk ch n ch n dio dio wake-up host cpu hiz hiz wake-up procedure ending figure-9 the timing diagram of pow er dow n command version: 1.3 july 31, 2003 10
SNAD02C 8-channel 10-bit adc (1) the power d o wn command (000/1 11) is sen t to SNAD02C in the fir s t three cycle s , and t hen SNAD02C enters into po wer down mode at t he 8 th clo ck cy cle , cons um ing a l m o st no curr ent (less than 1ua). (2) after SNAD02C enter s p o wer down ( m ode 0: co mmand 000) , SNAD02C send s ?0? ou t to dio until a valid log i c tra n s it ion ap pear s on any wakeup- enab le d digital input channe l. once the tran sit i on occur s , SNAD02C tog g les dio to ?1 ? to inform h o st co ntro ller . after re ceiving ?1? from dio , host contro ller sh ould t u rn start back to ?1? t o inf o rm SNAD02C that the power-down stage is over . othe rwise, SNAD02C keeps se ndin g out ?1? to d i o and doe s not recognize any other transitions on any channels. (3) after SNAD02C enter s p o wer down ( m ode 1: co mmand 111) , SNAD02C send s ?1? ou t to dio until a valid log i c tra n s it ion ap pear s on any wakeup- enab le d digital input channe l. once the tran sit i on occur s , SNAD02C tog g les dio to ?0 ? to inform h o st co ntro ller . after re ceiving ?0? from dio , host contro ller sh ould t u rn start back to ?1? t o inf o rm SNAD02C that the power-down stage is over . othe rwise, SNAD02C keeps se ndin g out ?1? to d i o and doe s not recognize any other transitions any the channels. (4) the clk ma y stop but st art ought t o remain at l o w level in t he who l e p o w er down m ode. (5) the SNAD02C provides two powe r-down mode ?power_down 0? and ?power_down 1?, user has to select a property power -down mode that it depend on what ki nd i/o type for host mcu (pul l-up or pull-low) before adc enter power-dow n mode. otherwise, it will gener ate a dc-path and the standby current also will go up. (6) before into power down mode, the ?rf? and ?mb? register must se t up ?0?, otherwise the standby current will more than 1ua. note: wakeu p f unction is only d edicated to t he chan nel w h ich is digita l input t y pe a nd wakeup - enabled. 6.7. bandgap reference vdd vss ref pad to refere nce hi gh of the adc rf mb 1.2v bandgap r e ference on chip of f chip figure-10 circuit diagram of adc bandgap reference selection version: 1.3 july 31, 2003 11
SNAD02C 8-channel 10-bit adc if the inter n a l band gap r e feren c e is tu rned on (rf=1), th e ref e rence volta ge ?vref? o f adc is from the int e rnal ban dg ap ref e ren c e cir c u i t. this int e rna l volt age re feren c e circu i t con s umes around 300 a, and the output voltage of bandgap reference is around 1.17v typically. if rf is turn ed of f (rf=0 ) , the mb is t u rned on (mb=1), th e re f e rence volt a ge is from ? r ef? pin . otherwise, the reference voltage source is comes from internal bandgap if rf=1 & mb=0. 6.8. input channel pad (channel 0~6) vdd vss ench[x] to adc di[x] ch[x] ench[x] pull-high resistor pull-low resistor ench[x]: 1: analog in / 0: digital in ph&ench[x] pl&ench[x] figure-11 circuit diagram of the input channel pad (1) if any chann el is progra mmed to be analog inpu t mode, t h e n the corr esponding inte rna l signal, ench[x]=1. as in figu re-11, pull-high and pull-low ar e disabled. and the path to digital input is blocked. all digital reading operation of this channel will get the result ?0?. (2) if any cha n n e l is prog ra mmed to dig i tal inp u t mode, the n the corre spon din g inter nal sig nal, ench[x]=0. as in figure-11, the path to adc is removed. (3) while in d i g i t a l inpu t mod e , th is input port ca n be conf igure d t o be flo a ting, weak pull-up , or pull-down by sett ing the contr o l r egist er ph and pl, where p h &pl=1 is f o rbid den. t he pull-up or pull-low resister are both around 500k ? @3v. (4) the d e fau l t status (d ig ital/ analo g , pull up/down) of all the chann els are un -kn o w aft e r p o wer on, so initialize each channel to define a correct state should be done after power on. (5) mode of each channel (ench[x]) can be set by command 001. version: 1.3 july 31, 2003 12
SNAD02C 8-channel 10-bit adc 6.9. battery monitoring (channel 7 only ) ench[7] to adc di[7] vss 20k 10k 30k vss battery ench[7] vdd vss ch[7] ph&ench[x] pl&ench[x] figure-12 the circuit of the input pad of channel 7 (1) while re ad adc command is sen t a n d chann el 7 is sele cte d , ad c can be u s e d to monit o r t he battery voltage. (2) the circuit of battery voltage monitoring is shown in figure-12 (channel7 only) (3) the ba ttery voltag e is six times adc measur ing vo lt age. t hus, t he measur ed resu lt e qua ls to 1/6*battery voltage. (4) while ch ann el 7 is set to t he ana log in put mode, a n input resist o r (60k ? ) exists from ch[7 ] to vss. to save unnecessary power consumption, ch[ 7] should be switch to digital input t y pe when ch[7] is not measured. note: ch[7 ] i s diffe r en t from the oth e r 7 cha n nels. th e inp u t v o ltage is red u c e d to 1/ 6 be for e it is sen t in to adc. version: 1.3 july 31, 2003 13
SNAD02C 8-channel 10-bit adc 7. electrical characteristics typical values apply for v dd =v ref =3.0 v, t amb =25 sy m b o l p a r a m e t e r m i n ty p m a x u n i t c o n d i t i o n s analog-to-digital converter v dd o p e r a t i n g v o l t a g e 2 . 7 3 . 0 5 . 2 5 v i dd o p e r a t i n g c u r r e n t 4 0 0 6 5 0 ? version: 1.3 july 31, 2003 14
SNAD02C 8-channel 10-bit adc 8. applica t ion circuits example circuit: SNAD02C w o rks w i th sonix 4-bit series controller ch[0], ch[1], ch[2]: analog input ch[6]: digital input ch[7]: battery voltage detect ref=vdd+ 4-bit voice chip p22 snad02 start clk dio vdd avdd ref vdd ` vss avss ch[0] ch[1] ch[7] analog signal 0.1u f vdd p21 p20 vss sn100/300/500 sn66/67/68/6a analog signal ch[2] analog signal ch[6] vdd figure-13 SNAD02C works with sonix 4-bit series controller version: 1.3 july 31, 2003 15
SNAD02C 8-channel 10-bit adc 9. example programs host controller: snc500. applic ation ci rcuit i s identical to fi gure11. p22: sta r t. p21: clk. p20: dio. macro programs: (def.h) i p2state equ m0 port_l equ m1 port_h equ m2 ad_out_l equ m3 ad_out_h equ m4 tmp equ m5 tmp1 equ m6 ad_hh equ m7 ;;******************************** @on_st art macro ;;set st art = 0 mov a #1011b and a p2state mov p2state a mov p2 a endm ;;******************************** @off_st art macro ;;set st art = 1 mov a #0100b or a p2state mov p2state a mov p2 a endm ;;******************************** @clock macro mov a #0010b ;;set clk l ? h and h ? l or a p2state mov p2 a mov a #1101b and a p2state mov p2state a mov p2 a endm ;;******************************** @send_0 macro mov a #1110b ;;host send 0 ? dio and a p2state mov p2state a mov p2 a endm ;;******************************** @send_1 macro mov a #0001b ;;host send 1 ? dio or a p2state mov p2state a mov p2 a endm ;;******************************** @send macro data ; ;host send 1-bit const a nt (#1 or #0) ? dio mov tmp data mov a #1110b and a p2state or a tmp mov p2state a mov p2 a endm version: 1.3 july 31, 2003 16 ;;********************************
SNAD02C 8-channel 10-bit adc @read_dio macro ;;read dio ? a.0 (1-bit ) mov a p2 mov tmp #0001b and a tmp endm ;;******************************** @p20_out_mode macro ; ;swit ch all 4-bit of p2 t o out p ut mode mov a #0000b mov p2s a endm ;;******************************** @p20_in_mode macro ; ;swit ch p2.0 (dio) t o input mode mov a #0001b mov p2s a mov a #1110b and a p2state mov p2state a mov p2 a endm ;;************************************************************************** ;; set analog/digital mode to each channel (1:analog, 0:digital) * ;; y 7 ? ch7. y 6 ? ch6. y 5 ? ch5, ? * ;;************************************************************************** @set_attrib macro y 7 ,y 6,y 5 ,y 4,y 3 ,y 2,y 1 ,y 0 @p20_out_mode ;; swit ch p2 t o out p ut mode @on_st art ;; set st art = 0 @s end_0 ;; send command (001) @clock @send_0 @clock @send_1 @clock @send y 7 ;; send y 7 t o y 0 @clock @send y 6 @clock @send y 5 @clock @send y 4 @clock @send y 3 @clock @send y 2 @clock @send y 1 @clock @send y 0 @clock @off_st art ;; set st art = 1 @p20_in_mode ;; swit ch p2.0 t o input mode endm version: 1.3 july 31, 2003 17
SNAD02C 8-channel 10-bit adc ;;************************************************************************* ;; set w a keup function enable/disable (1:enable, 0:disable) * ;; y 7 ? ch7. y 6 ? ch6. y 5 ? ch5, ? * ;;************************************************************************* @set_w akeup macro y 7 ,y 6,y 5 ,y 4,y 3 ,y 2,y 1 ,y 0 @p20_out_mode ;; swit ch p2 t o out p ut mode @on_st art ;; set st art = 0 @s end_0 ;; send command (010) @clock @send_1 @clock @send_0 @clock @send y 7 ;; send y 7 t o y 0 @clock @send y 6 @clock @send y 5 @clock @send y 4 @clock @send y 3 @clock @send y 2 @clock @send y 1 @clock @send y 0 @clock @off_st art ;; set st art = 1 @p20_in_mode ;; swit ch p2.0 t o input mode endm ;;********************************************************************** ;; setup control register * ;; ph: pull-high register. pl:pull-low register. * ;; rf: bandgap reference enable * ;; mb: set 0 alw a y s * ;;********************************************************************** @set_control_reg macro ph,pl,rf,mb @p20_out_mode ;; swit ch p2 t o out p ut mode @on_st art ;; set st art = 0 @s end_0 ;; send command (011) @clock @send_1 @clock @send_1 @clock @send ph ;; send ph, pl, rf, mb @clock @send pl @clock @send rf @clock @send mb @clock @off_st art ;; set st art = 1 @p20_in_mode ;; swit ch p2.0 t o input mode endm version: 1.3 july 31, 2003 18
SNAD02C 8-channel 10-bit adc ;;******************************************************************* ;; let SNAD02C enter pow e r-dow n mode 0 * ;;******************************************************************* @pow er_dow n_0 macro @p20_out_mode ;; swit ch p2 t o out p ut mode @on_st art ;; set st art = 0 @s end_0 ;; send command (000) @clock @send_0 @clock @send_0 @clock @p20_in_mode ;; swit ch p2.0 t o input mode @clock @clock @clock @clock @cloc k @clock @clock @cloc k ;; SNAD02C ent e rs power-down at t h e 8-th clock edge. endm ;;***************************************************************** ;; let SNAD02C enter pow e r-dow n mode 1 * ;;***************************************************************** @pow er_dow n_1 macro @p20_out_mode ;; swit ch p2 t o out p ut mode @on_st art ;; set st art = 0 @s end_1 ;; send command (111) @clock @send_1 @clock @send_1 @clock @p20_in_mode ;; swit ch p2.0 t o input mode @clock @clock @clock @clock @clock @clock @clock @cloc k ;; SNAD02C ent e rs power-down at t h e 8-th clock edge. endm ;;************************************************************************** ;; read adc from channel n (n= n2,n1,n0) ;; e.g.: ch 5 (n2, n1, n0= #1, #0, #1 ;; 10-bit data ? (ad_hh,ad_out_h, ad_out_l) ;; ad_hh is bit9~ b it8 , ad_out_h is bit7~ b it4 , ad_out_l is bit3~ b it0 ;;************************************************************************** @read_adc macro n0, n1, n2 @p20_out_mode ;; swit ch p2 t o out p ut mode @on_st art ;; set st art = 0 @send_1 ;; send command (100) @clock @send_0 @clock @send_0 @clock @send n2 ;; send channel number @clock @send n1 @clock version: 1.3 july 31, 2003 19
SNAD02C 8-channel 10-bit adc @send n0 @clock @p20_in_mode ;; swit ch p2.0 t o input mode @clock ;; wait for 2 more clocks @clock mov ad_out_l #0 mov ad_out_h #0 mov ad_hh #0 ;;*************************************** @cloc k ;; read dio and save 1-bit dat a in ad_hh.1 mov tmp1 #0010b @read_dio caje #0 @f mov a ad_hh or a tmp1 mov ad_hh a @@: ;;*************************************** @cloc k ;; read dio and save 1-bit dat a in ad_hh.0 mov tmp1 #0001b @read_dio caje #0 @f mov a ad_hh or a tmp1 mov ad_hh a @@: ;;*************************************** @cloc k ;; read dio and save 1-bit dat a in ad_out_h.3 mov tmp1 #1000b @read_dio caje #0 @f mov a ad_out_h or a tmp1 mov ad_out_h a @@: ;;*************************************** @cloc k ;; read dio and save 1-bit dat a in ad_out_h.2 mov tmp1 #0100b @read_dio caje #0 @f mov a ad_out_h or a tmp1 mov ad_out_h a @@: ;;*************************************** @cloc k ;; read dio and save 1-bit dat a in ad_out_h.1 mov tmp1 #0010b @read_dio caje #0 @f mov a ad_out_h or a tmp1 mov ad_out_h a @@: ;;*************************************** @cloc k ; ; read dio and save 1-bit dat a in ad_out_h.0 mov tmp1 #0001b @read_dio caje #0 @f mov a ad_out_h or a tmp1 mov ad_out_h a version: 1.3 july 31, 2003 20
SNAD02C 8-channel 10-bit adc @@: ;;*************************************** @cloc k ;; read dio and save 1-bit dat a in ad_out_l.3 mov tmp1 #1000b @read_dio caje #0 @f mov a ad_out_l or a tmp1 mov ad_out_l a @@: ;;*************************************** @cloc k ;; read dio and save 1-bit dat a in ad_out_l.2 mov tmp1 #0100b @read_dio caje #0 @f mov a ad_out_l or a tmp1 mov ad_out_l a @@: ;;*************************************** @cloc k ;; read dio and save 1-bit dat a in ad_out_l.1 mov tmp1 #0010b @read_dio caje #0 @f mov a ad_out_l or a tmp1 mov ad_out_l a @@: ;;*************************************** @clock ; ; read dio and save 1-bit dat a in ad_out_l.0 mov tmp1 #0001b @read_dio caje #0 @f mov a ad_out_l or a tmp1 mov ad_out_l a @@: ;;*************************************** @clock @off_st art ;; set st art = 1 endm ;;***************************************************************** ;; read digital input: * ;; 8-bit data ? (port_h, port_l) * ;;***************************************************************** @read_port macro @p20_out_mode ;; swit ch p2 t o out p ut mode @on_st art ;; set st art = 0 @s end_1 ;; set command (101) @clock @send_0 @clock @send_1 @clock @p20_in_mode ;; swit ch p2.0 t o input mode mov port_l #0 mov port_h #0 ;;*************************************** @clock ;; read dio and save 1-bit dat a in port_h.3 mov tmp1 #1000b @read_dio version: 1.3 july 31, 2003 21
SNAD02C 8-channel 10-bit adc caje #0 @f mov a port_h or a tmp1 mov port_h a @@: ;;*************************************** @clock ;; read dio and save 1-bit dat a in port_h.2 mov tmp1 #0100b @read_dio caje #0 @f mov a port_h or a tmp1 mov port_h a @@: ;;*************************************** @clock ;; read dio and save 1-bit dat a in port_h.1 mov tmp1 #0010b @read_dio caje #0 @f mov a port_h or a tmp1 mov port_h a @@: ;;*************************************** @clock ;; read dio and save 1-bit dat a in port_h.0 mov tmp1 #0001b @read_dio caje #0 @f mov a port_h or a tmp1 mov port_h a @@: ;;*************************************** @clock ;; read dio and save 1-bit dat a in port_l.3 mov tmp1 #1000b @read_dio caje #0 @f mov a port_l or a tmp1 mov port_l a @@: ;;*************************************** @clock ;; read dio and save 1-bit dat a in port_l.2 mov tmp1 #0100b @read_dio caje #0 @f mov a port_l or a tmp1 mov port_l a @@: ;;*************************************** @clock ;; read dio and save 1-bit dat a in port_l.1 mov tmp1 #0010b @read_dio caje #0 @f mov a port_l or a tmp1 mov port_l a @@: ;;*************************************** @clock ;; read dio and save 1-bit dat a in port_l.0 mov tmp1 #0001b @read_dio caje #0 @f mov a port_l or a tmp1 mov port_l a version: 1.3 july 31, 2003 22
SNAD02C 8-channel 10-bit adc @@: ;;*************************************** @clock @off_st art ;; set st art = 1 endm ;;*************************************** 9.1. program 1: set configuration of SNAD02C ;; setup configuration of SNAD02C ;; ;; w i th pull-low , use ?ref ? pin connected external voltage . (ph= 0, pl= 1 , rf = 0 ,mb= 1) ;; ;; ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 ;; analog/digital: b a a d d d a a :b, battery detect ;; w a keup: x x x no yes yes x x ;; snc520 program include def.h sta r t: mov a #1111b mov p2s a mov a #0000b mov p2 a mov p2state #0 @set_control_reg #0, #1, #0, #1 ;; set control registers 9.2 . program 2: read adc result from channel 1 ;; inherit from program 1 ;; 10-bit adc result of c hannel 1 in ( ad_hh,ad_out_h, ad_out_l) ;; ad_hh is bit9~ b it8, ad_out_h is bi t7~ b it4, ad_out_l is bit3~ b it0 @read_adc #0, #0, #1 ;;get adc result from ch1 in ( ad_hh,ad_out_h, ad_out_l) ? ? 9.3. program 3: read digital input data from ch4, ch3, ch2 ;; inherit from program 1 ;; after reading, ;; port_h.0 = input of ch4 ;; port_l.3 = input of ch3 ;; port_l.2 = input of ch2 @read_port ? (port_h, port_l) ? ? version: 1.3 july 31, 2003 23
SNAD02C 8-channel 10-bit adc 9.4. program 4: pow e r-dow n SNAD02C and host, and wake-up ;; inherit from program 1 ;; enter pow e r-dow n mode (0) @set_control_reg #0, #1, #0, #0 ;; set control registers rf and mb is 0 @pow er_dow n_0 ;;snad02 enters pow er-dow n mode (0) end ;; host (snc520) enter pow er dow n ? ? trigger: @off_st art ;; set st art = 1 ? @read_port ;; read t r igger condition or debounce procedure starting from here ? ? 9.5. program 5: battery low detection snc520 SNAD02C start clk dio vdd avdd ref vss avss ch[7] vdd 0.1uf vdd vdd vdd vss p20 p21 p22 vdd battery: 1.5vx3 an application uses three 1.5v batteries for power supply. during operation, the power of batteries keeps consumed and the voltage of battery keeps going down. now, voltage lower than 3.6v is treated as ?battery low?. the adc and band-gap reference circuit in snad02 can be utilized to detect ?battery low?. the voltage through ch annel 7 to a dc is reduced to 1/6*v dd (figure10). thus, when vdd=3.6v, the voltage into adc is around 0.6v. and bandgap is chosen for reference voltage (approximat ely 1.17v within the whole operation voltage range). the value acquired from adc is about (0.6/1.17)*256=131. for simplification consideration, we choose ?adc?s readout < 128? as ?battery low? condition. version: 1.3 july 31, 2003 24
SNAD02C 8-channel 10-bit adc ;; inherit from program 1 ;; enter pow e r-dow n mode (0) checkbattery : @set_control_reg #0, #1, #1, #0 ;; set rf= 1 , turn-on bandgap @ s e t _ a t t r i b #1, #1, #1, #0, #0, #0, #1, #1 ;; sw itch ch7 to analog mov m15 #0 checkagain: @read_adc #1, #1, #1 ;; read ch7 mov a #1000b and a ad_out_h c a j e #1000b battery _low _ n o ;; if (value> = 128) then not battery low mov a m15 inca mov m15 a c a j e # 3 battery _low _ y e s ;; if (value< 128) for 3 times, then jmp checkagain ;; battery low . battery _low _yes: mov m14 #1 battery _low _no: @set_control_reg #0, #1, #0, #0 ;; set rf= 0 , turn-off bandgap @ s e t _ a t t r i b #0, #1, #1, #0, #0, #0, #1, #1 ;; sw itch ch7 to digital ;; t o save operating current version: 1.3 july 31, 2003 25
SNAD02C 8-channel 10-bit adc 10. p ad diagram no pad name x ( um) y(um) no pad name x ( um) y(um) 1 c h 0 - 6 2 3 . 5 0 3 5 2 . 5 0 9 v s s 6 2 3 . 5 0 - 4 1 7 . 5 0 2 c h 1 - 6 2 3 . 5 0 2 4 2 . 5 0 1 0 v d d 6 2 3 . 5 0 - 3 0 7 . 5 0 3 c h 2 - 6 2 3 . 5 0 1 3 2 . 5 0 1 1 d i o 6 2 3 . 5 0 - 1 9 7 . 5 0 4 c h 3 - 6 2 3 . 5 0 2 2 . 5 0 1 2 c l k 6 2 3 . 5 0 - 8 7 . 5 0 5 c h 4 - 6 2 3 . 5 0 - 8 7 . 5 0 1 3 s t a r t 6 2 3 . 5 0 2 2 . 5 0 6 c h 5 - 6 2 3 . 5 0 - 1 9 7 . 5 0 1 4 a v d d 6 2 3 . 5 0 1 3 2 . 5 0 7 c h 6 - 6 2 3 . 5 0 - 3 0 7 . 5 0 1 5 v s s 6 2 3 . 5 0 2 4 2 . 5 0 8 c h 7 - 6 2 3 . 5 0 - 4 1 7 . 5 0 1 6 r e f 6 2 3 . 5 0 3 5 2 . 5 0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 1 2 10 vdd 11 dio 12 clk start 13 14 avdd 15 avss 16 ref 9 vss 3 4 5 6 7 8 (0,0) chip size=1350 x 950um snad02 note: the substrate must be c onnected to vss in pcb layout version: 1.3 july 31, 2003 26
SNAD02C 8-channel 10-bit adc version: 1.3 july 31, 2003 27 disclaimer the information appearing in sonix web pages (?this publicat ion?) is believed to be accurate. however, this publication could contain technical inaccuracies or typographical errors. the reader should not assume that this publication is e rror-free or that it will be suitable for any particular purpose. sonix makes no warr anty, express, statut ory implied or by description in this publication or other documents which are refe renced by or linked to this publication. in no event shall sonix be liabl e for any special, incidental, indirect or consequential damages of any kind, or any damages whatsoever, including, without limitation, those resulting from loss of use, data or profits, whether or not advised of the possibility of damage, and on any theory of liability, arising out of or in connection with the use or performance of this publication or other documents which are referenced by or linked to this publication. this publication was developed for products offe red in taiwan. sonix may not offer the products discussed in this document in other c ountries. information is subject to change without notice. please contac t sonix or its local repres entative for information on offerings available. integrat ed circuits sold by sonix ar e covered by the warranty and patent indemnification provisions sti pulated in the terms of sale only. the application circuits illustrated in this do cument are for refere nce purposes only. sonix disclaims all warranties, including the warranty of merchantability or fitness for any purpo se. sonix reserv es the right to halt production or alter the specifications and prices , and discontinue marketing the products listed at any ti me without notice. accordingly, th e reader is cautioned to verify that the data sheets and othe r information in this publicati on are current before placing orders. products described herein are intended for use in normal commercial applications. applications involving unusual environmental or reliability requirem ents, e.g. military equipment or medical life s upport equipment, are specifically not recommended without additional processing by sonix for such application.

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